Altera DE1-SoC GHRD
The Golden Hardware Reference Design (GHRD) for an Altera DE1-SoC Board.
Wishbone / Avalon Master
A small Bare Metal Cortex-A8 example using a Wishbone or Avalon Master
for a FPGA connection.
An independent JTAG-TAP is needed if you
does not want to use the JTAG system from your FPGA.
Quartus II and a DE1
Some notes for using Quartus II with an Altera DE1 Board.
N2IRvs is an Internet Radio which is supported by the Nios II, Nut/OS and a VS1053 decoder.
Nios II and Nut/OS
How to use Nut/OS on a Nios II based cpu on an Altera DE0-Nano Board.
Nios II and ChibiOS/RT
How to use ChibiOS/RT on a Nios II based cpu on an Altera DE1 Board.
Nios II and FatFs
Nios II and a generic FAT file system called FatFs.
Nios II and Qsys with a DE0-nano
Create your first Nios II project on an Altera DE0-Nano Development
Education Board with Qsys.
Movable Nios projects
How to create movable Nios projects.
Here you will find a collection of some Avalon Components which
are used in the projects.
These examples here can be used for a starting point for your own work. I will provide
small examples for the Altera DE1, DE0-Nano
and DE0-CV board.