This example is only a proof of concept to check if my GPMC to Wishbone / Avalon Master is
working. It does not use a SoC solution like the Cyclone V. In case of the hardware a BeagleBone
Black (Cortex-A8) and an Altera DE0-Nano (Cyclone IV) was used. For the software CrossWorks
for ARM (v2.3.5) for the CPU and Quartus II (11.1sp2) for the FPGA was involved.
Only the single read / write access mode will be supported.
If you are searching for a more powerful solution, take a look here at the
LOGIC Bone from ValentF(x).
For this example the following components was used:
All in all a dual Cortex-A8 solution could looks like:
The BeagleBone Black here is equipped with an external JTAG adapter. More information
about how to use an external JTAG adapter on the BeagleBone Black can be
There exist no schematic for the connection between the CPU and FPGA. For more information
take a look at the BeagleBone Black System Reference Manual and the FPGA source. Remember,
only 16-bit accesses are supported by the actual FPGA design.
LED0 to LED6 of the DE0-Nano can be controlled by the GPIO-0 slave. Also the output of
GPIO-0 is connected to the input of GPIO-1.
A major advantage of the CrossWorks for ARM solution is that the CPU and SDRAM is being
initialized before the actual start of the debugging session. Therefore it is possible to
load the application into the external SDRAM. This is realized by load and execute of a
Sitara StarterWare "Bootloader" before the application to debug.
It is a Bare Metal application, therefore no RTOS is used. Instead the Sitara StarterWare
is also used for the application to setup and initialize some parts of the CPU. The example
here does not contain a full version of the StarterWare. For a full AM335x version take a look
at the following TI page.
For the connection between the CPU and the FPGA the GPMC controller of the CPU is used.
From the point of view by the CPU the FPGA is an external 16-bit non-multiplexed memory
mapped device. Only 16-bit accesses are supported by the actual FPGA design.
The implementation here is based on the "Wishbone Specification Version B3".
The FPGA design contains the following Wishbone
- wb_syscon: Wishbone SYSCON for the DE0-Nano
- gpmc_wb_master: GPMC / Wishbone Master, supports classic bus cycles (single read / write)
- wb_intercon: Wishbone Interconnection (one master, multiple slaves)
- wb_gpio: simple GPIO slave
Compared to the Wishbone Master it was easier to create the system because of the help from the
functionality of Qsys. Here the interconnection of each device will be done by the Qsys system.
In case of the Wishbone Master the interconnection must be created by yourself.
Be careful with the wait signal from the Avalon bus. The following info was found in the Altera
application note "AN-397 Interfacing to External Processors":
After the master deasserts the read/write signal, the waitrequest signal asserts again
after one Avalon clock cycle to signify the Avalon bus is ready for another read or write
transfer from the master.
Remember, the GPMC (gpmc) signals are negative active and the Avalon (avm) are positive active.
This is a read access where the Avalon waitrequest is active from the beginning. The Avalon switch
fabric reads data from the slave component and latches the data to drive out the data bus. The
waitrequest signal is deasserted at this time (marker 1). After the master deasserts the read signal,
the waitrequest signal asserts again (marker 2).
This will make problems if the CPU and Avalon signals will be connected directly together. To
solve this problem here, the state machine from the Wishbone Master was used with some small
Wishbone Specification Version B3 (898 KB)
DE0-Nano Wishbone design de0n-gpmc-wb_20151107 (32 KB, for Quartus II 11.1sp2)
DE0-Nano Avalon design de0n-gpmc-av_20170604 (98 KB, for Quartus II 11.1sp2)
BeagleBone Black Wishbone application b3-gpmc-wb_20151107 (272 KB)
BeagleBone Black Avalon application b3-gpmc-av_20170604 (290 KB)