Independent JTAG-TAP
Introduction
Hardware
Software
Download
 

Introduction

If you want to use JTAG in your design, but not the integrated JTAG system by your FPGA, then you need an additional independent JTAG-TAP. In case of the example here, the FPGA is controlled by the onboard Altera USB-Blaster, and the design by an additional JTAG. The additional JTAG is connected through the GPIO-1 port.

Hardware

For this project an Altera DE1 Board was used:

The following connections are needed for the secondary JTAG on the GPIO-1 port:

  • Pin 30 = VTref (3.3V)
  • Pin 14 = nTRST
  • Pin 16 = TDI
  • Pin 18 = TMS
  • Pin 01 = TCK
  • Pin 22 = RTCK   (not used here)
  • Pin 24 = TDO
  • Pin 26 = RESET   (not used here)
  • Pin 30 = GND

Note: Pin 01 of the GPIO-1 port must connected with the "EXT CLK" (J5) too.

Software

For testing the design SignalTap II, a real Logic Analyzer and UrJTAG version 0.10 was used.

After downloading and install the UrJTAG program, some additional files must be copied into the "data" folder of UrJTAG. These files "de1", "de1user1" and "de1user2" could be found in the "urjtag" folder of the Quartus project.

Note: Here I am using an Amontec JTAGkey for testing. If you use an other JTAG adapter, "de1" must be changed.

To set up the UrJTAG program the "de1" file must be included after the UrJTAG start. After including the "de1" file, the response will look like:

jtag> include de1
Connected to libftd2xx driver.
IR length: 4
Chain length: 1
Device Id: 01101101011010010110011001101001 (0x000000006D696669)
  Unknown manufacturer!
chain.c(149) Part 0 without active instruction
chain.c(200) Part 0 without active instruction
chain.c(149) Part 0 without active instruction
jtag>

The example project use two user register, "user1" and "user2".

The "user1" register has a width of 8 bit. And will be used to write data to the first 2 segments of the 7-segments display. At the same time the switch0 to switch7 are read back. The "user2" register has a with of 4 bit. And will be used to write data to the third segment of the 7-segments display. At the same time the key0 to key3 are read back. The fourth segment of the 7-segments display will show the JTAG instruction register value.

To write 0xC9 to the "user1" register and read back the switch information, include the "de1user1" file. The response will look like:

jtag> include de1user1
11001001
10000110
jtag>

Here 0x86 was read back from the switches.

Even there exist a file for the "user2" register, "de1user2". The example will write 0x7 to the "user2" register and read back the keys. The respons will look like:

jtag> include de1user2
0111
0000
jtag>

Here 0x0 was read back from the keys.

For more information about the use of UrJTAG take a look in the UrJTAG manual (UrJTAG.txt).

Download

Quartus de1_jtag_test_20140914 project for the Altera DE1 board (28 KB)