QSB4088com (Babel fish)
lwIP-µHTTP (PoC)
Wishbone Master


"The Babel fish is small, yellow, leech-like, and probably the oddest thing in the universe. It feeds on brain wave energy, absorbing all unconscious frequencies and then excreting telepathically a matrix formed from the conscious frequencies and nerve signals picked up from the speech centres of the brain, the practical upshot of which is that if you stick one in your ear, you can instantly understand anythingsaid to you in any form of language: the speech you hear decodes the brain wave matrix."

It is a universal translator that neatly crosses the language divide between any species.
(Source: "The Hitchhiker’s Guide to the Galaxy" Wikipedia)

Here the "Babel fish" is a communication solution established by a Quick Start Board from Embedded Artists and a self made base board.


The QSB4088com solution provides a lot of functionality:

  • Cortex-M4 (QSB4088 from Embedded Artists)
  • Ethernet
  • USB-A host interface
  • USB-micro-B device interface
  • 2 independent CAN channels
  • RS232 interface
  • RS485 or RS422 interface
  • UART-TTL interface (FTDI)
  • MMC/SD interface

If you want to have more functionality, take a look at the LPC4088 Developers's Kit.


In general the TinyCTS/AL "RTOS" is used for the examples here. And we will start with the Blinky-CAN example.


"tcts-tal-blinky-bf4088" is not only a blinky. Additional for each CAN channel an echo server was implemented. Any message which is send to a CAN channel will be send back. The echo server will support standard and extended messages.

bf4088-blinky-can_20180829 Blinky-CAN example (983 KB)

lwIP-µHTTP (PoC)

This example here is more a Proof of Concept than a full featured application. More background information can be find at my TinyCTS/AL - lwIP - µHTTP example.

bf4088-tcts-lwip_20180829 lwIP-µHTTP example (2.41 MB)


EtherNet/IP(TM) is an industrial Ethernet network that combines standard Ethernet technologies with the media-independent Common Industrial Protocol or "CIP." EtherNet/IP is one of the leading industrial Ethernet networks in the world and is widely used in a range from industries including factory, hybrid and process. The EtherNet/IP and CIP technologies are managed by ODVA, Inc., a global trade and standards development organization founded in 1995 whose over 300 corporate members are the world leading automation device suppliers. [Source: Wikipedia]

The Common Industrial Protocol (CIP) is an industrial protocol for industrial automation applications. It is supported by ODVA. [Source: Wikipedia]

OpENer is an EtherNet/IP stack for I/O adapter devices. It supports multiple I/O and explicit connections and includes objects and services for making EtherNet/IP compliant products as defined in the ODVA specification.

Credits goes to Alois Zoitl of fortiss and Martin Melik-Merkumians from the Automation and Control Institute (ACIN) of the Vienna University of Technology who have supported me.

OpENer source: opener-master-v120_20150116 (253 KB)

OpENer patch: opener-master-v120_20150116_patch (6 KB)

Example: bf4088-tcts-opener-11_20180829 (2.68 MB)

Wishbone Master

The implementation here is based on the "Wishbone Specification Version B3". The FPGA design contains the following Wishbone components:

  • wb_syscon: Wishbone SYSCON for the DE0-Nano
  • spi_wb_master: SPI / Wishbone Master, supports classic bus cycles (single read / write)
  • wb_intercon: Wishbone Interconnection (one master, multiple slaves)
  • wb_gpio: GPIO slave
  • wb_timer: Timer slave
  • wb_test: TEST slave (a test register set)

Compared to my other Wishbone example, this one uses the SPI bus (SSP0) to communicate with the FPGA.

Wishbone Specification Version B3 (898 KB)

DE0-Nano Wishbone design de0n-spi-wb_20171228 (34 KB, for Quartus II 11.1sp2)

"Babel fish" Wishbone application bf4088-spi-fpga_20171228 (847 KB)